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High Performance Wide Input Range Dual Synchronous Buck Controller
POWER MANAGEMENT Description
The SC2544 is a high performance dual PWM controller. It is designed to convert a wide ranged input voltage down to two independent output rails. The PWM operations of the two channels are 180 degree out of phase which can greatly reduce the size and the cost of the input capacitors. Synchronous Buck PWM topology and voltage mode control allow high efficiency operation, fast transient responses, and flexible component selection for easy designs. A 10V internal linear regulator provides the bias for the controller, and this voltage is optimized for gate drivers to deliver high efficiency. The power sequencing is fully supported including independent start up, and power good output. In the shut down mode the controller only draws 100nA from the supply. The controller also offers full protection features for the conditions of under voltage, over voltage, and the over current. There is no need for a current sensing resistor because the MOSFET on resistance is used for the sensing element. The switching frequency is adjustable from 100 kHz to 300 kHz. Two packages TSSOP-24 and MLPQ24 are offered.
SC2544
Features
Independent dual-outputs Wide input voltage range: 4.5V~28V Adjustable output voltage down to 0.75V Flexible power sequencing with enable and power good output Synchronous Buck topology with voltage mode control Out of phase operation to reduce cost of input capacitor 10V internal regulator for gate driver to deliver high efficiency Programmable switching frequency:100kHz~300kHz Full protection: UVLO, OVP and programmable OCP No need for current sense resistor Low shutdown current (100nA typical) 24 lead TSSOP and MLPQ packages Fully WEEE and RoHS Compliant
Applications
Systems with 4.5V~28V input LCDTV and PDPTV Network and telecom systems Portable devices
Typical Application Circuit
SC2544
VIN+ VCC VO1 1 2 3 4 5 VIN+ 6 7 8 VO1 9 10 11 FB1 12 VIN VCC EN FB1 ERROUT1 SS1 ILIM1 BST1 DRVH1 PHASE1 DRVL1 PGND AGND ROSC PWRGD FB2 ERROUT2 SS2 ILIM2 BST2 DRVH2 PHASE2 DRVL2 PVCC 24 23 22 21 20 19 18 17 16 15 14 13 VCC FB2 VO2 VIN+ PWGRD FB2
ENABLE FB1
Pinout shown as TSSOP-24.
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SC2544
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter BST1, BST2 to PGND VIN to PGND ILIM1, ILIM2 and EN to PGND VC C and PVC C to PGND PGND to AGND BST1 to PH1, BST2 to PH2, D RVH1 to PH1, D RVH2 to PH2 D RVL1, D RVL2 to PGND PHASE, D RVL to AGND pulse (100nS), peak voltage All Other Pi ns to AGND Storage Temperature Range Juncti on Temperature Lead Temperature (Solderi ng) 10 Sec for TSSOP-24 Lead Temperature (IR Reflow) for MLPQ-24 Thermal Resi stance Juncti on to C ase TSSOP-24 MLP-24 Thermal Resi stance Juncti on to Ambi ent TSSOP-24 MLP-24
Symbol V b st Vin
Maximum 38 28 VIN 14 +/- 0.3 -0.3 to 14 -0.3 to VC C -3 -0.3 to VC C
U nits V V V V V V V V V
o o
TSTG TJ TLEAD JC
-60 to +150 -40 to +150 260 23 2 78 25
o
C C C
o
C /W
JA
o
C /W
Note: This device is ESD sensitive. Use of standard ESD handling precautions is required.
Electrical Characteristics
Unless specified: TA = 25 C, VIN=16V, Fs=200KHz .
o
Parameter U ndervoltage Lockout Start Threshold UVLO Hysteresi s Pow er Supply Operati ng C urrent (I IN-IPVCC) Vcc Regulated Vcc Load Regulati on Level Vcc Li ne Regulati on PVcc Operati ng C urrent D i sable Qui escent C urrent Main Sw itcher output Li ne Regulati on Load Regulati on Output Voltage Accuracy
Test C onditions
Min
Typ
Max
U nit
Vcc ri si ng Vcc falli ng 200
4.5
V mV
SS1/SS2/EN =Hi gh, FS=200kHz VIN > 12V I_load=0~20mA Vi n=12~24V 200KHz, 1nF on HG, 1nF on LG EN=low
6.0 10 2 2 14 0.1
10
mA V % % mA
10
uA
5V0.5 0.5 0.750 0.765
% % V
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SC2544
POWER MANAGEMENT Electrical Characteristics Unless specified: T = 25 C, V =16V, Fs=200KHz (Cont.)
o A IIN
Parameter ENABLE EN Ramp Up Threshold Voltage EN Ramp Down Threshold Voltage Soft Start Soft Start Charge Current Soft Start Discharge Current Threshold Voltage for DRVL Out of Tri-State Error Amplifier Voltage Feedback Reference Input Bias Current Open Loop Gain
(1)
Test Conditions
Min
Typ
Max
Unit
2 0.6
V V
84 15 Pull below this level, turning on DRVL (Turn on low side MOSFET) 0.65
uA uA V
TA = -40oC to +85oC
0.735
0.750
0.765 2
V uA dB MHz mA V/uS nS
70 3 1 100pF capacitive loading
(1)
Unity Gain Bandwidth (1) Output Source/Sink Current Slew Rate
(1)
10 75
PWM Comparator to Output Delay Oscillator Frequency Range per phase Oscillator Frequency per phase Oscillator Ramp Peak Voltage Oscillator Ramp Valley Voltage Current Limit ILIM Source Current ILIM Offset Voltage Duty Cycle PWM 1 & 2 Maximum Duty Cycle PWM 1 & 2 Minimum Duty Cycle
100 Rosc=73K OHM 175 210 2.3 1
300 245
kHz kHz V V
9
10 2
11
uA mV
Rosc = 73K OHM Rosc = 73K OHM
90 0
% %
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SC2544
POWER MANAGEMENT Electrical Characteristics Unless specified: T = 25 C, V =16V, Fs=200KHz (Cont.)
o A IN
Parameter Driver DRVH1, DRVH2 Drive Current DRVL1, DRVL2 Drive Current Gate Drive Rise Time (10% to 90%) Gate Drive Fall Time (90% to 10%) Dead Time OVP OVP Threshold Voltage P o w er g o o d Threshold Voltage Threshold Voltage Power Good Pull Down
Test Conditions
Min
Typ
Max
Units
Source/Sink Source/Sink Vcc=10V, COUT = 1000pF Vcc=10V, COUT = 1000pF
0.5 0.5 30 30 80
A A nS nS nS
Feedback voltage
0.89
V
FB1 & FB2 rising FB1 & FB2 falling Sink 1mA
0.675 0.57 0.4
V V V
Note: (1) Guaranteed by design.
Ordering Information
Part Number SC2544TSTRT(1),(2) SC2544MLTRT(1),(2) P ackag e TSSOP-24 MLPQ-24 Temp. Range (TA) -40oC to +85oC -40oC to +85oC
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free package. Device is fully WEEE and RoHS compiant.
Pin Configurations
Top View
VI N AG ND RO SC VCC PW R G D
VI N VC C EN FB 1 E R R O U T1 SS1 II 1 LM B S T1 D R VH1 PH ASE1 D R V L1 PG N D
Top View
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
AG ND R O SC PW R G D FB 2 E R R O U T2 SS2 II 2 LM B S T2 D R VH2 PH ASE2 D R V L2 PVCC
FB 1 E R R O U T1 SS1 II 1 LM B S T1 DR VH1
EN
1 24
19
FB 2 E R R O U T2 SS2 II 2 LM B S T2
7
D R V L2 D R V L2 PVCC PG ND PG ND D R V L1 PH ASE1 PH ASE1
13
DR VH2
PH ASE2
24 PIN TSSOP
MLPQ-24
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SC2544
POWER MANAGEMENT Pin Descriptions for SC2544TSTRT (TSSOP)
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name VIN VC C EN FB 1 ERROUT1 SS1 ILIM1 BST1 DRVH1 PHASE1 DRVL1 PGND PVC C DRVL2 PHASE2 DRVH2 BST2 ILIM 2 SS2 ERROUT2 FB 2 PWRGD ROSC AGND Pin Function Input supply voltage. The range is from 4.5V to 28V. 10V regulator output. Supply voltage for the gate drivers. Connect to VIN pin when Vin<10V. When EN pin is low all outputs are disabled. Typical shutdown current is l00nA. Negative input of the error amplifier for output1. Error amplifier output for buck converter1. An external capacitor connected from this pin to AGND sets the soft-start time. Disable output1 by pulling this pin below 1V. An external resistor connected from this pin to PHASE1 sets the over current shutdown trip point. Boost capacitor connection for output1 high side gate drive. Connect an external capacitor as shown in the typical application circuit. Gate drive for the high side MOSFET of output1. 180 degrees out of phase with DRVH2. Phase node for output 1. Low side gate drive for output 1. Power ground of low-side drivers. Supply voltage for low-side gate drivers. Low-side gate drive for output 2. Phase node for output 2. Gate drive for the high side MOSFET of OUTPUT2. 180 degrees out of phase with DRVH1. Boost capacitor connection for OUTPUT2 high side gate drive. Connect an external capacitor as shown in the typical application circuit. An external resistor connected from this pin to PHASE2 sets the over current shutdown trip point. An external capacitor connected from this pin to AGND sets the soft-start time. Disable output1 by pulling this pin below 1V. Error amplifier output for buck converter2. Negative input of the error amplifier of output2. Open collector output. It is internally pulled low when either output is below the power good threshold level. A resistor from this pin to AGND sets oscillator frequency. Analog signal ground. Star connected to the system ground plane.
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SC2544
POWER MANAGEMENT Pin Descriptions for SC2544MLTRT (MLPQ)
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name FB 1 ERROUT1 SS1 ILIM1 BST1 DRVH1 PHASE1 DRVL1 PGND PVC C DRVL2 PHASE2 DRVH2 BST2 ILIM2 SS2 ERROUT2 FB 2 PWRGD ROSC AGND VIN VC C EN Pin Function Negative input of the error amplifier for output1. Error amplifier output for buck converter1. An external capacitor connected from this pin to AGND sets the soft-start time. Disable output1 by pulling this pin below 1V. An external resistor connected from this pin to PHASE1 sets the over current shutdown trip point. Boost capacitor connection for output1 high side gate drive. Connect an external capacitor as shown in the typical application circuit. Gate drive for the high side MOSFET of output1. 180 degrees out of phase with DRVH2. Phase node for output 1. Low side gate drive for output 1. Power ground of low-side drivers. Supply voltage for low-side gate drivers. Low-side gate drive for output 2. Phase node for output 2. Gate drive for the high side MOSFET of output2. 180 degrees out of phase with DRVH1. Boost capacitor connection for output2 high side gate drive. Connect an external capacitor as shown in the typical application circuit. An external resistor connected from this pin to PHASE2 sets the over current shutdown trip point. An external capacitor connected from this pin to AGND sets the soft-start time. Disable output1 by pulling this pin below 1V. Error amplifier output for buck converter2. Negative input of the error amplifier of output2. Open collector output. It is internally pulled low when either output is below the power good threshold level. A resistor from this pin to AGND sets oscillator frequency. Analog signal ground. Star connected to the system ground plane. Input supply voltage. The range is from 4.5V to 28V. 10V regulator output. Supply voltage for the gate drivers. Connect to VIN pin when Vin<10V. When EN pin is low all outputs are disabled. Typical shutdown current is 100nA.
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SC2544
POWER MANAGEMENT Block Diagram (One PWM channel
shown)
PVCC
BST1
Protect 1
DRVH1 PHASE1
Ramp1 ROSC Oscillator Ramp generator CLK1
+ PWM S R Q
PHASE1 PVCC
PVCC DRVL1
Protect 1
ERROUT1 FB1 FB1 + OUT 3R R 0.75V + S UVLO OCP VCC VCC VIN OVP OUT ENABLE 0.75V Band Gap 1 10V LDO Band Gap 2 0.75V 0.675V FB1 FB2 + OUT OVP OCP 0.89V + FB1 OUT + /Q Protect 1 10u A ILIM1 E/A OUT OUT R 0.75V + VCC
SS1
EN
ON/OFF VCC UVLO
PWRGD
AGND
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SC2544
POWER MANAGEMENT Applications Information
Overview The SC2544 is a constant frequency 2-phase voltage mode step-down PWM switching controller driving all N-channel MOSFETs. The two channels of the controller operate at 180 degree out of phase from each other. Since input currents are interleaved in a two-phase converter, input ripple current is lower and smaller input capacitance can be used for filtering. Also, with lower inductor current and smaller inductor ripple current per phase, overall I2 R losses are reduced. Frequency Setting The frequency of the SC2544 is userprogrammable.The oscillator of SC2544 can be programmed with an external resistor from the Rosc pin to the ground. The step-down controller is capable of operating up to 300KHz. The relationship between oscillation frequency versus oscillation resistor is shown in Figure 1. The advantages of using constant frequency operation are simple passive component selection and ease of feedback compensation. Before setting the operating frequency, the following trade-offs should be considered. 1) Passive component size 2) Circuitry efficiency 3) EMI condition 4) Minimum switch on time 5) Maximum duty ratio For a given output power, the sizes of the passive components are inversely proportional to the switching frequency, whereas MOSFETs/Diodes switching losses are proportional to the operating frequency. Other issues such as heat dissipation, packaging and cost issues are also to be considered. The frequency bands for signal transmission should be avoided because of EM interference.
350 300 Fsw(KHz) 250 200 150 100 50 40 50 60 70 80 90 Rosc (KOHM) 100 110 120 130 140 150 160 170 180
Soft Start During start-up, the reference voltage of the error amplifier equals 30% of the voltage on Css (softstart capacitor) which is connected between the SS pin and ground. When the controller is enabled (by pulling EN pin high), one internal 84uA current source, I SS, (soft start current) will charge the softstart capacitor gradually. The PWM output starts pulsing when the soft start voltage reaches 1V. This soft start scheme will ensure the duty cycle to increase slowly, therefore limiting the charging current into the output capacitor and also ensuring the inductor does not saturate. The soft start capacitor will eventually be charged up to 2.5V. The soft-start sequence is initiated when EN pin is high and Vcc >4.5V or during recovery from a fault condition ( OCP, OVP, or UVLO). The period of start up can be programed by the soft start capacitor:
Tss =
Css x 2.5V 84 A
Shutdown When the EN pin is pulled low, an internal 15uA current source discharges the soft-start capacitor and DRVH/DRVL signals stop pulsing. The output voltage ramps down at a rate determined by the load condition. The SC2544 can also be shutdown by pulling down directly on the SS pin. The designer needs to consider the slope of the SS pin voltage and choose a suitable pull down resistor to prevent the output from undershooting. Shutdown can also be triggered when an OCP condition occurs. When an OCP condition is detected, DRVH and DRVL will stop pulsing and enter a "tristate shutdown" with the output voltage ramping down at a rate determined by the load condition. The internal 15uA current source will begin discharging the soft-start capacitor and when the soft-start voltage reaches 0.65V, DRVL will go high.
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Figure 1. Switching frequency versus Rosc.
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SC2544
POWER MANAGEMENT Applications Information (Cont.)
Over Current Protection (OCP) The inductor current is sensed by using the low side MOSFET Rds(on) . After low side MOSFET is turned on, the OCP comparator starts monitoring the voltage drop across the MOSFET. The OCP trip level is programmed by the resistor from the ILIM pin to the phase node. There is an internal current source that flows out of the ILIM pin which will generate a voltage drop on the setting resistor. When the sum of the setting resistor voltage and the MOSFET drain to source voltage is less then zero, the OCP condition will be flagged. This functionality is depicted in Figure 2. The following formula is used to set the OCP level
TG IL
100n S B lan kin g
O C P A ctive
Figure 3. OCP comparator timing chart. Voltage (UVLO) U nder Voltage Lock Out (UVL O) The UVLO circuitry monitors Vcc and the soft start begins once Vcc ramps up above 4.5V. There is a built in 200mV hysteresis for the UVLO ramp down threshold. The gate driver output will be in "tristate" (both high side and low side MOSFET off) once Vcc ramps down bellow 4.2V (typical), and the soft start cap will be discharged by internal 15uA current sink. Over Voltage Pro (OVP) Ov er Voltage Pr o t ection (O VP) The OVP circuitry monitors the feedback voltages, If either feedback voltage exceeds 0.89V, the OVP condition is registered. Under this condition, the DRVH pins will be pulled low, and the DRVL pins will be pulled high. This will create a "crow bar" condition for the input power rail in case the high side MOSFET is failed short. The crow bar operation may trip the input supply to prevent the load from seeing more voltage. P o w er Good Output
10 A x RILIM = I L _ PEAK x RDS ( ON )
When OCP is tripped, both high side and low side MOSFETs will be turned off and this condition is latched. At the same time, the soft start cap will be discharged by the internal current source of 15uA. When the Vss drops bellow 0.65V, the DRVL pin will go high again. To avoid switching noise during the phase node commutation, a 100nS blanking time is built in after the low side MOSFET is turned on, as shown in Fig. 3.
VCC 10uA
DRVH ILIM DRVL
OUTPUT
OCP Out
+
-
Figure 2. Block diagram of over current protection.
The power good is an open collector output. The PWRGD pin is pulled low at start up if any of the two feedback voltages below 90% of its regulation level. The ramp down threshold of the signal is 80% of the regulation target. External pull up is required for the PWRGD pin, and the pull up resistor should be chosen such that the pin does not sink more than 2mA when PWRGD is low.
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SC2544
POWER MANAGEMENT Applications Information (Cont.)
Procedure for Step-do ep-down Po General Design Pr ocedure f or a St ep-do wn P o w er Converter Selection criterias and design procedures for the following parameters are described: 1) Output inductor (L) type and value 2) Output capacitor (C o) type and value 3) Input capacitor (C in) type and value 4) Power MOSFETs 5) Current sensing and limiting circuit 6) Voltage sensing circuit 7) Loop compensation network The following step-down converter specifications are needed: Input voltage range: V in,min and V in,max Input voltage ripple (peak-to-peak): DV in Output voltage: V o Output voltage accuracy: e Output voltage ripple (peak-to-peak): DV o Nominal output (load) current: I o Maximum output current limit: I o,max Output (load) current transient slew rate: dIo (A/ s) Circuit efficiency: Inductor (L) and Ripple Current Both step-down controllers in the SC2544 operate in synchronous continuous-conduction mode (CCM) regardless of the output load level. The output inductor selection/design is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductance but it takes longer to change the inductor current during load transients. Conversely smaller inductance results in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple-current is 20% to 30% of the rated output load current. Assuming that the inductor current ripple (peak-topeak) value is *Io, the inductance value will then be
L= Vo (1 - D) . Io fs
IL,rms = Io 1 +
2 . 12
The followings are to be considered when choosing inductors. a) Inductor core material: For higher efficiency applications above 300 KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores can be used for cost sensitiveapplications below 300 KHz but with attendant higher core losses. b) Select inductance value: Sometimes the calculated inductance value is not available off-the-shelf. The designer can choose the adjacent (larger) standard inductance value. The inductance varies with temperature and DC current. It is a good engineering practice to re-evaluate the resultant current ripple at the rated DC output current. c) Current rating: The saturation current of the inductor should be at least 1.5 times of the peak inductor current under all conditions. Capacitor Output Capacit or (C o) and V out Ripple The output capacitor provides output current filtering in steady state and serves as a reservoir during load transient. The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR and ESL as shown in Figure 4.
Co
Lesl
Resr
Figure 4. An equivalent circuit of output. If the current through the branch is ib(t), the voltage across the terminals will then be
vo (t) = Vo +
The peak current in the inductor becomes (1+ /2)*Io and the RMS current is
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di (t) 1 ib (t)dt + Lesl b + Resrib (t). Co 0 dt
t
This basic equation illustrates the effects of ESR, ESL, and Co on the output voltage.
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SC2544
POWER MANAGEMENT Applications Information (Cont.)
The first term is the DC voltage across C o at time t=0. The second term is the voltage variation caused by the charge balance between the load and the converter output. The third term is voltage ripple due to ESL and the fourth term is the voltage ripple due to ESR. The total output voltage ripple is then a vector sum of the last three terms. Since the inductor current is a triangular waveform with peak-to-peak value G *I o , the ripple-voltage caused by inductor current ripples is
The voltage rating of aluminum capacitors should be at least 1.5Vo. The RMS current ripple rating should also be greater than
G,R
Usually it is necessary to have several capacitors of the same type in parallel to satisfy the ESR requirement. The voltage ripple caused by the capacitor charge/discharge should be an order of magnitude smaller than the voltage ripple caused by the ESR. To guarantee this, the capacitance should satisfy
&R ! SIV5 HVU
'Y& |
G,R &RIV
G ,R '
the ripple-voltage due to ESL is
' Y (6/
and the ESR ripple-voltage is
/ HVO I V
In many applications, several low ESR ceramic capacitors are added in parallel with the aluminum capacitors in order to further reduce ESR and improve high frequency decoupling. Because the values of capacitance and ESR are usually different in ceramic and aluminum capacitors, the following remarks are made to clarify some practical issues. Remark 1: High frequency ceramic capacitors may not carry most of the ripple current. It also depends on the capacitor value. Only when the capacitor value is set properly, the effect of ceramic capacitor low ESR starts to be significant. For example, if a 10 P F, 4m : ceramic capacitor is connected in parallel with 2x1500 P F, 90m : electrolytic capacitors, the ripple current in the ceramic capacitor is only about 42% of the current in the electrolytic capacitors at the ripple frequency. If a 100 P F, 2m : ceramic capacitor is used, the ripple current in the ceramic capacitor will be about 4.2 times of that in the electrolytic capacitors. When two 100 P F, 2m : ceramic capacitors are used, the current ratio increases to 8.3. In this case most of the ripple current flows in the ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output ripple-voltage. Remark 2: The total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. The total equivalent ESR is not simply the parallel combination of all the individual ESRs either. Instead they should be calculated using the following formula.
&HT &HT ZZ
11
'Y(65
5HVUG,R
Aluminum capacitors (e.g. electrolytic) have high capacitances and low ESLs. The ESR has the dominant effect on the output ripple voltage. It is therefore very important to minimize the ESR. Other types to choose are solid OS-CON, POSCAP, and tantalum. When determining the ESR value, both the steady state ripple-voltage and the dynamic load transient need to be considered. To meet the steady state output ripple-voltage spec, the ESR should satisfy
5H VU
To limit the dynamic output voltage overshoot/ undershoot within a (say 3%) of the steady state output voltage from no load to full load, the ESR value should satisfy
'92 G ,2
5H VU
92 ,2
Then, the required ESR value of the output capacitors should be Resr = min{Resr1,Resr2 }.
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5D &D 5E &E Z &D &E &D &E
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5D 5E Z &D &E &D &E

SC2544
POWER MANAGEMENT Applications Information (Cont.)
5 Z &HTHT Z 5D5E 5D 5E Z &D &E 5E &E 5D &D 5D 5E Z &D &E &D &E

where R 1a and C 1a are the ESR and capacitance of electrolytic capacitors, and R 1b and C1b are the ESR and capacitance of the ceramic capacitors, respectively (Figure 5).
In Figure 6 the DC input voltage source has an internal impedance Rin and the input capacitor Cin has an ESR of R esr . MOSFET and input capacitor current waveforms, ESR voltage ripple and input voltage ripple are shown in Figure 7.
L 4
&D 5D &E 5E &HT 5HT
L &LQ 9HVU
Figure 5. Equivalent RC branch. Req and Ceq are both functions of frequency. For rigorous design, the equivalent ESR should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. If R1a = R1b = R1 and C1a = C1b = C1, then R eq and Ceq will be frequency-independent and Req = 1/2 R1 and Ceq = 2C1. Input Capacitor (Cin) The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input capacitors are needed to filter the current pulses at the switching frequency. A simple buck converter is shown in Figure 6.

9&LQ
Figure 7. Typical waveforms at converter input. It can be seen that the current in the input capacitor pulses with high di/dt. Capacitors with low ESL should be used. It is also important to place the input capacitor close to the MOSFETs on the PC board to reduce trace inductances around the pulse current loop. The RMS value of the capacitor current is approximately
,&LQ ,R '> G ' ' ' @ K K
The power dissipated in the input capacitors is then PCin = ICin2Resr. For reliable operation, the maximum power dissipation in the capacitors should not result in more than 10oC of temperature rise. Many manufacturers specify the maximum allowable ripple current (ARMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. It is common pratice that multiple capacitors are placed in parallel to increase the ripple current handling capability.
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5LQ
5HVU
' &R 5R
9'&
&LQ
Figure 6. A simple model for the converter input.
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SC2544
POWER MANAGEMENT Applications Information (Cont.)
Sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is
v ESR = R esr (1 + )Io . 2
The peak-to-peak input voltage ripple due to the capacitor is
v C DIo , Cin fs
Po MOSFETs Choosing Power MOSFETs Main considerations in selecting the MOSFET's are power dissipation, MOSFETs cost, and packaging. Switching losses and conduction losses of the MOSFET's are directly related to the total gate charge (C g) and channel on-resistance (R ds(on)). In order to judge the performance of MOSFET's, the product of the total gate charge and on-resistance is used as a figure of merit (FOM). Transistors with the same FOM follow the same curve in Figure 8.
From these two expressions, CIN can be found to meet the input voltage ripple specification. In a multi-phase converter, channel interleaving can be used to reduce ripple. The two step-down channels of the SC2544 operate at 180 degrees from each other. If both stepdown channels in the SC2544 are connected to the same input rail, the input RMS currents will be reduced. Ripple cancellation effect of interleaving allows the use of smaller input capacitors. When two channels with a common input are interleaved, the total DC input current is simply the sum of the individual DC input currents. The combined input current waveform depends on duty ratio and the output current waveform. Assuming that the output current ripple is small, the following formula can be used to estimate the RMS value of the ripple current in the input capacitor. Let the duty ratio and output current of Channel 1 and Channel 2 be D1, D2 and Io1, Io2, respectively. If D1<0.5 and D2<0.5, then
ICin D1Io1 + D 2Io2 .
2 2
50 Gate Charge (nC) 40 Cg( 100 , Rds ) Cg( 200 , Rds ) Cg( 500 , Rds ) 20
1
0
0 1
5
10
15
20 20
FOM:100*10^{-12} FOM:200*10^{-12} FOM:500*10^{-12}
Rds On-resistance (mOhm)
Figure 8. Figure of Merit curves. The closer the curve is to the origin, the lower is the FOM. This means lower switching loss or lower conduction loss or both. It may be difficult to find MOSFET's with both low C g and low R ds(on. Usually a trade-off between R ds(on and Cg has to be made. MOSFET selection also depends on applications. In many applications, either switching loss or conduction loss dominates for a particular MOSFET. For synchronous buck converters with high input to output voltage ratios, the top MOSFET is hard switched but conducts with very low duty cycle. The bottom switch conducts at high duty cycle but switches at near zero voltage. For such applications, MOSFET's with low Cg are used for the top switch and MOSFET's with low R ds(on) are used for the bottom switch. MOSFET power dissipation consists of a) conduction loss due to the channel resistance Rds(on); b) switching loss due to the switch rise time t r and fall time t f; and c) the gate loss due to the gate resistance RG.
If D1>0.5 and (D1-0.5) < D2<0.5, then
ICin 0.5Io1 + (D1 - 0.5)(Io1 + Io 2 )2 + (D 2 - D1 + 0.5)Io 2 .
2 2
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
ICin 0.5Io1 + D 2 (Io1 + Io 2 )2 + (D1 - D 2 - 0.5)Io 2 .
2 2
If D1>0.5 and D2 > 0.5, then
ICin (D1 + D 2 - 1)(Io1 + Io 2 )2 + (1 - D 2 )Io1 + (1 - D1 )Io2 .
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SC2544
POWER MANAGEMENT Applications Information (Cont.)
Switch Top Switc h The RMS value of the top switch current is calculated as 2 IQ1,rms = Io D(1+ 12 ). The conduction losses are then P tc = I Q1,rms 2 R ds(on). R ds(on) varies with temperature and gate-source voltage. Curves showing Rds(on) variations can be found in manufacturers' data sheet. From the Si4860 datasheet, Rds(on) is less than 8m when Vgs is greater than 10V. However R ds(on) increases by 50% as the junction temperature increases from 25oC to 110 oC. The switching losses can be estimated using the simple formula
1 Pts = 2 ( t r + t f )(1 + 2 )Io Vin fs .
In Figure 9, Qgs1 is the gate charge needed to bring the gate-to-source voltage Vgs to the threshold voltage V gs_th. Q gs2 is the additional gate charge required for the switch current to reach its full-scale value Ids, and Qgd . is the charge needed to charge gate-to-drain (Miller) capacitance when Vds is falling. Switching losses occur during the time interval [t 1, t3]. Defining tr = t3-t 1 and tr can be approximated as
tr = (Q gs 2 + Q gd )R gt Vcc - Vgsp .
where Rgt is the total resistance from the driver supply rail to the gate of the MOSFET. It includes the gate driver internal impedance Rgi, external resistance Rge and the gate resistance Rg within the MOSFET : R gt = Rgi+R ge+R g. Vgsp is the Miller plateau voltage shown in Figure 9. Similarly an approximate expression for tf is
tf = (Q gs 2 + Q gd )R gt Vgsp .
where tr is the rise time and tf is the fall time of the switching process. Different manufactures have different definitions and test conditions for t and r t . To clarify these, we sketch the typical MOSFET f switching characteristics under clamped inductive mode in Figure 9.
V ds V o lts Ids M iller plateau V gs
Only a portion of the total losses P g = Q g V cc f s is dissipated in the MOSFET package. Here Q g is the total gate charge specified in the datasheet. The power dissipated within the MOSFET package is
Rg R gt
Ptg =
Q g Vcc fs .
V gs th
The total power loss of the top switch is then Pt = Ptc+Pts+Ptg.
Q gs1 Q gs2 t0 t1 t2
Q gd t3 G ate charge
Figure 9. MOSFET switching characteristics
If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction losses are inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design.
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SC2544
POWER MANAGEMENT Applications Information (Cont.)
Bottom Switch The RMS current in bottom switch is given by
IQ2,rms = Io (1- D)(1+ 12 ).
2
The conduction losses are then P bc=I Q2,rms2 R ds(on) . where R ds(on) is the channel resistance of bottom MOSFET. If the input voltage to output voltage ratio is high (e.g. V in =12V, V o=1.5V), the duty ratio D will be small. Since the bottom switch conducts with duty ratio (1-D), the corresponding conduction losses can be quite high. Due to non-overlapping conduction between the top and the bottom MOSFET's, the internal body diode or the external Schottky diode across the drain and source terminals always conducts prior to the turn on of the bottom MOSFET. The bottom MOSFET switches on with only a diode voltage between its drain and source terminals. The switching loss is negligible due to near zerovoltage switching. The gate losses are estimated as
P bg = Rg R gt Q g V cc f s .
Main Control Loop Design The goal of compensation is to shape the frequency response charatericstics of the buck converter to achieve a better DC accuracy and a faster transient response for the output voltage, while maintaining the loop stability. The block diagram in Figure 10 represents the control loop of a buck converter designed with the SC2544. The control loop consists of a compensator, a PWM modulator, and an LC filter. The LC filter and PWM modulator represent the small signal model of the buck converter operating at fixed switching frequency. The transfer function of the model is given by:
VO VIN 1 + sRESRC = VC Vm 1 + sL / R + s 2 LC
REF REF
+ EA -
PWM
MODULATOR
L
Vo
Co
Zf Zs ERROUT
Resr
The total bottom switch losses are then Pb=Pbc+Pbg. Once the power losses for the top and bottom MOSFET's are known, thermal and package design at component and system level should be done to verify that the maximum die junction temperature (T j,max , usually 125 o C) is not exceeded under the worst-case condition. The equivalent thermal impedance from junction to ambient ( ja ) should satisfy
ja Tj,max - Ta,max Ploss .
Fig. 10. Block diagram of the control loop. where VIN is the input voltage, Vm is the amplitude of the internal ramp, and R is the equivalent load. The model is a second order system with a finite DC gain, a complex pole pair at Fo, and an ESR zero at Fz, as shown in Figure 11. The locations of the poles and zero are determined by:
packaging material, the thermal contact surface, thermal compound property, the available effective heat sink area, and the air flow condition (natual or forced convection). Actual temperature measurement of the prototype should be carried out to verify the thermal design.
2005 Semtech Corp. 15
ja depends on the die to substrate bonding,
FO =
1 2 LCO
1 2 Re srCO
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FZ =
SC2544
POWER MANAGEMENT Applications Information (Cont.)
The compensator in Figure 10 includes an error amplifier and impedance networks Zf and Zs. It is implemented by the circuit in Figure 12. The compensator provides an integrator, double poles, and double zeros. As shown in Figure 11, the integrator is used to boost the gain at low frequency. Two zeros are introduced to compensate excessive phase lag at the loop gain crossover due to the integrator (-90deg) and the complex pole pair (-180deg). Two high frequency poles are designed to compensate the ESR zero and to attenuate high frequency noise. A resistive divider is used to program the output voltage. The top resistor Rtop of the divider in Fig. 12 can be chosen from 20k to 30k . Then the bottom resistor Rbot is found from:
Rbot =
0.75V Rtop Vo - 0.75V
Fp1
C O M P E N S A TO R G A I N
Fp2
G A I (d B ) N
F z1 Fo
F z2
LO
OP GA I N
CO
Fz
NV
Fc
ER TE RG A IN
F R E Q U E N C Y (H z)
Fig. 11. Bode plots for control loop design.
where 0.75V is the internal reference voltage of the SC2544. The other components of the compensator can be calculated using following design procedure: (1). Plot the converter gain, including LC filter and PWM modulator. (2). Select the open loop crossover frequency Fc located at 10% to 20% of the switching frequency. At Fc, find the required DC gain. (3). Use the first compensator pole Fp1 to cancel the ESR zero Fz. (4). Have the second compensator pole Fp2 at half the switching frequency to attenuate the switching ripple and high frequency noise. (5). Place the first compensator zero Fz1 at or below 50% of the power stage resonant frequency Fo. (6). Place the second compensator zero Fz2 at or below the power stage resonant frequency Fo. A MathCAD program is available upon request for the calculation of the compensation parameters.
C2 C1 R2 C3 R3
Rtop
Vc
Out
Vo
-
E/A
+ Rbot 0.75V
Fig. 12. Compensation network.
2005 Semtech Corp.
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SC2544
POWER MANAGEMENT Applications Information (Cont.)
PC Board Layout Issues Circuit board layout is very important for the proper operation of high frequency switching power converters. A power ground plane is required to reduce ground bounces. The followings are suggested for proper layout. P o w er Stage 1) Separate the power ground from the signal ground. In SC2544 design, use an isolated local ground plane for the controller and tie it to power grand. 2) Minimize the size of the high pulse current loop. Keep the top MOSFET, the bottom MOSFET and the input capacitors within a small area with short and wide traces. In addition to the aluminum energy storage capacitors, add multi-layer ceramic (MLC) capacitors from the input to the power ground to improve high frequency bypass. 3) Reduce high frequency voltage ringing. Widen and shorten the drain and source traces of the MOSFETs to reduce stray inductances. Add a small RC snubber if necessary to reduce the high frequency ringing at the phase node. Sometimes slowing down the gate drive signal also helps in reducing the high frequency ringing at the phase node if the EMI is a concern for the system. 4) Shorten the gate drive trace. Integrity of the gate drive (voltage level, leading and falling edges) is important for circuit operation and efficiency. Short and wide gate drive traces reduce trace inductances. Bond wire inductance is about 2~3nH. If the length of the PCB trace from the gate driver to the MOSFET gate is 1 inch, the trace inductance will be about 25nH. If the gate drive current is 2A with 10ns rise and falling times, the voltage drops across the bond wire and the PCB trace will be 0.6V and 5V respectively. This may slow down the switching transient of the MOSFET's. These inductances may also ring with the gate capacitance. 5) Put the decoupling capacitor for the gate drive power supplies (BST and PVCC) close to the IC and power ground. Control Section 6) The frequency-setting resistor Rosc should be placed close to Pin 23. Trace length from this resistor to the analog ground should be minimized. 7) Place the bias decoupling capacitor right across the VCC and analog ground AGND.
2005 Semtech Corp.
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SC2544
POWER MANAGEMENT Typical Application Circuit SC2544MLTRT
U1 C1 C2 EN FB1 C3 C9 1n SS1 18k 4.7K N.P. C17 1uF/16V R8 R10 2.2 VIN+ 0 C10 220nF 1uF/25V 1uF/16V VIN+ 1 VCC 2 3 4 5 6 7 8 9 10 11 12 VIN VCC EN FB1
SC2544
AGND ROSC PWRGD FB2 24 23 22 21 20 19 18 17 16 15 14 13 C31 1uF/16V VCC IRF7811A VIN+ C18 R9 1uF/16V 0 470nF C11 SS2 R5 R7 C33 R3 73K
VO2
R2
10K PWGRD FB2 C4 1n 18k 4.7k n.p. R11 C12 4.7n
ERROUT1 ERROUT2 SS1 ILIM1 BST1 DRVH1 PHASE1 DRVL1 PGND R24 SS2 ILIM2 BST2 DRVH2 PHASE2 DRVL2 PVCC
4.7n R4 R6 C32
2.2
C5 N.P.
C6 10uF/25V
C7
C8 Q2 IRF7811A
Q1
C13
C14 0.1uF/25V
C15
C16 N.P.
10uF/25V 0.1uF/25V
0R
10uF/25V 10uF/25V
VO1
L1
7.6uH IRF7811A Q3 IRF7811A Q4
L2
7.6uH R13 499 C35 N.P. 330uF/6.3V 330uF/6.3V R25 N.P. N.P. N.P. C24 C25 C26 C27 R14
VO2
R12 28K R15 499 FB1 C19 3.9nF R17 4.9K C20 C21 C22 C23
C34 N.P.
C29 C30 N.P. 2.2nF
28K C28 3.3nF
FB2
N.P. N.P. 330uF/6.3V 330uF/6.3V
R25 N.P.
R18 4.9K
Vin: 4.5V ~ 28V Vout: 3.3V/6A and 5V/6A
2005 Semtech Corp.
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SC2544
POWER MANAGEMENT Evaluation Board - Bill of Material SC2544MLTRT Reference R ef Qty
1 2 3 4 1 3 4 14 C1 C2,C18,C31 C3,C4,C34,C35 L1, L2, C 5, C 16, C 20, C 21, C 24, C 24, C 30, C32, C33,R25 C 6, C 7, C 14, C 15 C 8, C 13 C 12, C 9 C 10, C11 C 17 C28,C19 C 22, C 23, C 26, C 27 L1, L2 Q1, Q2, A3, Q4 R2 R3 R5, R4 R6 R7 R10 R25, R11 R14, R12 R15,R13 R18, R17 R24 U1
Part Number/Value Any Any Any
Manufacturer
1uF, 25V, X5R,Ceramic, 0805 1uF, 16V, X5R, Ceramic , 0805 1nF, Ceramic 0805 N.P.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
4 2 2 1 1 1 2 2 2 4 1 1 2 1 1 1 1 2 2 2 1 1
10uF, 25V, X5R , Ceramic 1206 0.1uF, 25V, 0603 4.7nF, Ceramic, 0603 220nF, Ceramic, 0603 470nF, Ceramic, 0603 1nF, Ceramic, 0603 3.3nF, Ceramic, 0603 33uF, 6.3V, 18mohm, PosCap 7.6uH, 6.8A, 16mohm IRF7811A 10K , 0603 73.2K, 0603 18K , 0603 6.8K, 0603 4.7K, 0603 4.7, 0603 4.7, 0603 2.2, 0603 499, 0603 4.9K, 0603 0, 0603 S C 2544
Panasonic, ECJ3YB1E106M Any Any Any Any Any Any Sanyo, 6TPE330MIL Sumida, CDRH127 IR Any Any Any Any Any Any Any Any Any Any Any Semtech
2005 Semtech Corp.
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SC2544
POWER MANAGEMENT Typical Characteristics
C C C C H H H H 1:T G 2:B G 3:T G 4:B G 1 1 2 2
CH CH CH CH
1 :V 2 :V 3 :V 4 :V
i en SS o
G a t w a ve f rm e o
Shut down by pulling down EN pin voltage.
CH1:TG CH2:BG CH3:VSS CH4:Vo
C H 3:V o C H 4:Io
Start up.
Transient response(0-5A).
CH CH CH CH
1:V 2:V 3:V 4:V
i cc SS o
C C C C
H H H H
1 :T G 2 :B G 3 :T G 4 :B G
Shutdown by pulling down SS pin voltage.
2005 Semtech Corp. 20
Over current protection (5A/10mV)
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SC2544
POWER MANAGEMENT Typical Characteristics (Cont.)
Vin=8V 100% Fs (khz) 80% Efficient 60% 40% 20% 0% 0 1 2 3 4 5 6 Io(A) 7 8 9 10 Vin=16V 190 188 186 184 182 180 178 -40 -10 20 50 80 110
Temperature (Degree C)
Efficiency Curve for Vout=3.3V.
Freq. vs. Temp. ( Rosc=75kohm, Vin=16V).
350 300 Fsw(KHz) 200 150 100 50 40 50 60 70 80 90 Rosc(KOHM) 100 110 120 130 140 150 160 170 180 250
10.5 10.3 Vcc (V) 10.1 9.9 9.7 9.5 10 12 14 16 18 20 22 24 26 28 30 Vin (V)
Operating frequency vs. Rosc.
Vcc vs. Vin ( Ta=25 Degree C).
9 8
Vcc (V)
10.13 10.11 10.09 10.07 10.05 10.03 -40 -20 0 20 40 60 80 100 120 Tj (Degree C)
Io(A)
7 6 5 4 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 RILIM(KOHM)
RILIM vs. OCP (Vi=12V).
Vcc vs. Temp.
2005 Semtech Corp.
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SC2544
POWER MANAGEMENT Typical Characteristics (Cont.)
7.0 6.5 Icc (mA) 6.0 5.5 5.0 8 10 12 14 16 18 Vin(V) 20 22 24 26 28
Icc vs. Vin (25 DegreeC).
DRVL min Ton(nS)
500 480 460 440 420 400 -40 -20 0 20 40 60 80 100 120 Tj (Degree C)
DL min Ton vs. Tj (Vin=16V).
100 Dead time (nS) 80 60 40 20 0
-40
-20
0
20
40
60
80
100
120
Tj (Degree C)
Dead time vs. Tj (Vin=16V, DH falling to DL rising).
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SC2544
POWER MANAGEMENT Outline Drawing - TSSOP-24
DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .007 .012 .003 .007 .303 .307 .311 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 24 0 8 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 7.70 7.80 7.90 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 24 0 8 0.10 0.10 0.20
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123
D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
E
e/2 B
aaa C SEATING PLANE
D A2 A
C bxN bbb
A1 C A-B D GAGE PLANE 0.25
H c
L (L1) DETAIL
01
SIDE VIEW
SEE DETAIL
A
A
NOTES: 1. 2. 3. 4. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -HDIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MO-153, VARIATION AD.
Land Pattern - TSSOP-24
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2005 Semtech Corp. 23 www.semtech.com
SC2544
POWER MANAGEMENT Outline Drawing - MLPQ-24 (4 x 4mm)
A D B
DIM
A A1 A2 b D D1 E E1 e L N aaa bbb
Top View
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 D1 LxN E/2 C SEATING PLANE
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .031 .035 .040 0.80 0.90 1.00 .000 .001 .002 0.00 0.02 0.05 - (0.20) - (.008) .007 .010 .012 0.18 0.25 0.30 .151 .157 .163 3.85 4.00 4.15 .100 .106 .110 2.55 2.70 2.80 .151 .157 .163 3.85 4.00 4.15 .100 .106 .110 2.55 2.70 2.80 0.50 BSC .020 BSC .011 .016 .020 0.30 0.40 0.50 24 24 .004 0.10 .004 0.10
Bottom View
E1 2 1 N e D/2
bxN bbb CAB
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPQ-24 (4 x 4mm)
K
(C)
H
G
Z
DIM C G H K P X Y Z
DIMENSIONS INCHES MILLIMETERS (.155) (3.95) 3.10 .122 .106 2.70 .106 2.70 .021 0.50 .010 0.25 .033 0.85 .189 4.80
X P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2005 Semtech Corp.
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